NY8A051E 6 I/O 8-bit EPROM-Based MCU
關鍵詞： NY8A051E 8位微控制器 EPROM 內(nèi)存結構
NY8A051E 6 I/O 8-bit EPROM-Based MCU
1. 概述
NY8A051E是以EPROM作為記憶體的 8 位元微控制器，專為多IO產(chǎn)品的應用而設計，例如遙控器、風扇/燈光控制或是遊樂器周邊等等。採用CMOS製程並同時提供客戶低成本、高性能等顯著優(yōu)勢。NY8A051E核心建立在RISC精簡指令集架構可以很容易地做編輯和控制，共有 55 條指令。除了少數(shù)指令需要 2 個時序，大多數(shù)指令都是 1 個時序即能完成，可以讓使用者輕鬆地以程式控制完成不同的應用。因此非常適合各種中低記憶容量但又複雜的應用。在I/O的資源方面，NY8A051E有 6 根彈性的雙向I/O腳，每個I/O腳都有單獨的暫存器控制為輸入或輸出腳。而且每一個I/O腳位都有附加的程式控制功能如上拉或下拉電阻或開漏極(Open-Drain) 輸出。此外針對紅外線搖控的產(chǎn)品方面，NY8A051E內(nèi)建了可選擇頻率的紅外載波發(fā)射口。
NY8A051E有兩組計時器，可用系統(tǒng)頻率當作一般的計時的應用或者從外部訊號觸發(fā)來計數(shù)。另外NY8A051E提供 1組 8 位元解析度的PWM輸出或者蜂鳴器輸出，可用來驅(qū)動馬達、LED、或蜂鳴器等等。
NY8A051E採用雙時鐘機制，高速振盪或者低速振盪都由內(nèi)部RC振盪輸入。在雙時鐘機制下，NY8A051E可選擇多種工作模式如正常模式(Normal)、慢速模式(Slow mode)、待機模式(Standby mode) 與睡眠模式(Halt mode)可節(jié)省電力消耗延長電池壽命。並且微控制器在使用內(nèi)部RC高速振盪時，低速振盪可以同時使用外部精準的Crystal32768Hz 來計時。可以維持高速處理同時又能精準計算真實時間。在省電的模式下如待機模式(Standby mode)與睡眠模式(Halt mode)中，有多種事件可以觸發(fā)中斷喚醒NY8A051E進入正常操作模式(Normal) 或 慢速模式(Slow mode) 來處理突發(fā)事件。
NY8A051E內(nèi)建低速晶振 (32768Hz) 電容，CL有Disable、7pF、9pF、12.5pF四種選項可選，方便客戶減少外部零件，仍可得到較精準的PPM值。
NY8A051E在 PB1/PB2 內(nèi)建大驅(qū)動電流模式(20mA@3V, 34mA@5V)，提供客戶大電流需求。且在 PB3(Vpp) 增加內(nèi)部上拉電阻 85K歐姆，並可由程式控制開關。
1.1 功能
? 寬廣的工作電壓：(指令週期為 4 個CPU clock，亦即 4T模式)
? 2.0V ~ 5.5V @系統(tǒng)頻率≦8MHz。
? 2.2V ~ 5.5V @系統(tǒng)頻率＞8MHz。
? 寬廣的工作溫度：-40°C ~ 85°C。
? 1Kx14 bits EPROM。
? 48 bytes SRAM。
? 6 根可分別單獨控制輸入輸出方向的I/O腳(GPIO)、PB[5:0]。
? PB[3:0]可選擇輸入時使用內(nèi)建下拉電阻，當輸入時可以使用上拉電阻。
? PB[5:4]及PB[2:0]可選擇上拉電阻或開漏極輸出(Open-Drain)。
? PB[3]可選擇當作輸入或開漏極輸出(Open-Drain)。
? 8 層程式堆棧(Stack)。
? 存取資料有直接或間接定址模式。
? 一組 8 位元上數(shù)計時器(Timer0)包含可程式化的頻率預除線路。
? 一組 8 位元下數(shù)計時器(Timer1)可選重複載入或連續(xù)下數(shù)計時。
? 一個 8 位元的脈衝寬度調(diào)變輸出(PWM1)。
? 一個蜂鳴器輸出(BZ1)。
? 38/57KHz 紅外線載波頻率可供選擇，同時載波之極性也可以根據(jù)數(shù)據(jù)作選擇。
? 內(nèi)建上電復位電路(POR)。
? 內(nèi)建低壓復位功能(LVR)。
? 內(nèi)建看門狗計時(WDT)，可由程式韌體控制開關。
? 雙時鐘機制，系統(tǒng)可以隨時切換高速振盪或者低速振盪。
? 高速振盪: I_HRC (1~20MHz內(nèi)部高速RC振盪)
? 低速振盪: I_LRC (內(nèi)部 32KHz低速RC振盪)
E_LXT (外部 32KHz低速石英振盪)
? 四種工作模式可隨系統(tǒng)需求調(diào)整電流消耗：正常模式(Normal)、慢速模式(Slow mode)、待機模式(Standby
mode) 與 睡眠模式(Halt mode)。
? 五種硬體中斷：
? Timer0 溢位中斷。
? Timer1 借位中斷。
? WDT 中斷。
? PB 輸入狀態(tài)改變中斷。
? 外部中斷輸入。
? NY8A051E在待機模式(Standby mode)下的五種喚醒中斷：
? Timer0 溢位中斷。
? Timer1 借位中斷。
? WDT 中斷。
? PB 輸入狀態(tài)改變中斷。
? 外部中斷輸入。
? NY8A051E在睡眠模式(Halt mode)下的三種喚醒中斷：
? WDT 中斷。
? PB 輸入狀態(tài)改變中斷。
? 外部中斷輸入。
1.1 Features
? Wide operating voltage range: (@ 4 CPU clock per instruction, i.e. 4T mode)
? 2.0V ~ 5.5V @system clock ≦8MHz.
? 2.2V ~ 5.5V @system clock ＞8MHz.
? Wide operating temperature: -40°C ~ 85°C.
? 1K x 14 bits EPROM.
? 48 bytes SRAM.
? 6 general purpose I/O pins (GPIO), PB[5:0], with independent direction control.
? PB[3:0] have features of Pull-Low and Pull-High resistor for input pin.
? PB[5:4] and PB[2:0] have features of Pull-High resistor, and open-drain output.
? PB[3] have feature of input or open-drain output.
? 8-level hardware Stack.
? Direct and indirect addressing modes for data access.
? One 8-bit up-count timer (Timer0) with programmable prescaler.
? One 8-bit reload or continuous down-count timers (Timer1).
? One 8-bit resolution PWM (PWM1) output.
? One buzzer (BZ1) output.
? Selectable 38/57KHz IR carrier frequency and high/low polarity according to data value.
? Built-in Power-On Reset (POR).
? Built-in Low-Voltage Reset (LVR).
? Built-in Watch-Dog Timer (WDT) enabled/disabled by firmware control.
? Dual-clock oscillation: System clock can switch between high oscillation and low oscillation.
? High oscillation: I_HRC (Internal High Resistor/Capacitor Oscillator ranging from 1M~20MHz)
? Low oscillation: I_LRC (Internal 32KHz oscillator)
E_LXT (External Low Crystal Oscillator, 32768Hz)
? Four kinds of operation mode to reduce system power consumption:
? Normal mode, Slow mode, Standby mode and Halt mode.
? Five hardware interrupt events:
? Timer0 overflow interrupt.
? Timer1 underflow interrupt.
? WDT timeout interrupt.
? PB input change interrupt.
? External interrupt.
? Five interrupt events to wake-up NY8A051E from Standby mode:
? Timer0 overflow interrupt.
? Timer1 underflow interrupt.
? WDT timeout interrupt.
? PB input change interrupt.
? External interrupt.
? Three interrupt events to wake-up NY8A051E from Halt mode:
? WDT timeout interrupt.
? PB input change interrupt.
? External interrup
1.2 Block Diagram
2. Memory Organization
NY8A051E memory is divided into two categories: one is program memory and the other is data memory.
2.1 Program Memory The program memory space of NY8A051E is 1K words. Therefore, the Program Counter (PC) is 10-bit wide in order to address any location of program memory. Some locations of program memory are reserved as interrupt entrance. Power-On Reset vector is located at 0x000. Software interrupt vector is located at 0x001. Internal and external hardware interrupt vector is located at 0x008. NY8A051E provides instruction CALL, GOTOA, CALLA to address 256 location of program space. NY8A051E provides instruction GOTO to address 512 location of program space. NY8A051E also provides instructions LCALL and LGOTO to address any location of program space. When a call or interrupt is happening, next ROM address is written to top of the stack, when RET, RETIA or RETIE instruction is executed, the top of stack data is read and load to PC. NY8A051E program ROM address 0x3FE~0x3FF are reserved space, if user tries to write code in these addresses will get unexpected false functions. NY8A051E program ROM address 0x00E~0x00F are preset rolling code can be released and used as normal program space.
2.2 Data Memory
According to instructions used to access data memory, the data memory can be divided into three kinds ofcategories: one is R-page Special-function Register (SFR) + General Purpose Register (GPR), another isF-page SFR and the other is S-page SFR. GPR are made of SRAM and user can use them to store variablesor intermediate results.
R-page data memory is divided into 4 banks and can be accessed directly or indirectly through a SFR registerwhich is File Select Register (FSR). FSR[7:6] are used as Bank register BK[1:0] to select one bank out of the 4banks.
R-page register can be divided into addressing mode: direct addressing mode and indirect addressing mode.
The indirect addressing mode of data memory access is described in the following graph. This indirect addressing mode is implied by accessing register INDF. The bank selection is determined by FSR[7:6] and thelocation selection is from FSR[5:0].
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